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| JPEG 2000 Video Codec ADV212 FEATURES Complete single-chip JPEG 2000 compression and decompression solution for video and still images Identical in pinout and footprint to the ADV202 and supports all the functionality of the ADV202 Power reduction of at least 30% compared with ADV202 JTAG/boundary scan support Patented SURF(R) (spatial ultraefficient recursive filtering) technology enables low power, low cost wavelet-based compression Supports both 9/7 and 5/3 wavelet transforms with up to 6 levels of transform Video interface directly supporting ITU-R BT.656, SMPTE 125M PAL/NTSC, SMPTE 274M, SMPTE 293M (525p), and ITU-R BT.1358 (625p), or any video format with a maximum input rate of 65 MSPS for irreversible mode or 40 MSPS for reversible mode Programmable tile/image size with widths up to 4096 pixels in single-component mode; maximum tile/image height: 4096 pixels 2 or more ADV212s can be combined to support full-frame SMPTE 274M HDTV (1080i) or SMPTE 296M (720p) Flexible, asynchronous SRAM-style host interface allows glueless connection to most 16-/32-bit microcontrollers and ASICs 2.5 V or 3.3 V input/output and 1.5 V core supply 12 mm x 12 mm, 121-ball CSPBGA with a speed grade of 115 MHz, or 13 mm x 13 mm, 144-ball CSPBGA with a speed grade of 150 MHz GENERAL DESCRIPTION The ADV212 is a single-chip JPEG 2000 codec targeted for video and high bandwidth image compression applications that can benefit from the enhanced quality and features provided by the JPEG 2000 (J2K)--ISO/IEC15444-1 image compression standard. The part implements the computationally intensive operations of the JPEG 2000 image compression standard and provides fully compliant code-stream generation for most applications. The dedicated video port of the ADV212 provides glueless connection to common digital video standards such as ITU-R BT.656, SMPTE 125M, SMPTE 293M (525p), ITU-R BT.1358 (625p), SMPTE 274M (1080i), or SMPTE 296M (720p). A variety of other high speed, synchronous pixel and video formats can also be supported by using the programmable framing and validation signals. The ADV212 is an upgrade version of the ADV202 that is identical in pinout and footprint. It supports all the functionality of the ADV202 and has the following additional options: * * JTAG/boundary scan support Power reduction of at least 30% compared with the ADV202 APPLICATIONS Networked video and image distribution systems Wireless video and image distribution Image archival/retrieval Digital CCTV and surveillance systems Digital cinema systems Professional video editing and recording Digital still cameras Digital camcorders FUNCTIONAL BLOCK DIAGRAM PIXEL I/F PIXEL I/F EXTERNAL DMA CTRL HOST I/F PIXEL FIFO CODE FIFO ATTR FIFO EMBEDDED RISC PROCESSOR SYSTEM INTERNAL BUS AND DMA ENGINE WAVELET ENGINE EC1 EC2 EC3 ADV212 Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved. 06389-001 RAM ROM ADV212 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 JPEG 2000 Feature Support......................................................... 3 Specificatons...................................................................................... 4 Supply Voltages and Current ...................................................... 4 Input/Output Specifications........................................................ 4 Clock and RESET Specifications ................................................ 5 Normal Host Mode--Write Operation ..................................... 6 Normal Host Mode--Read Operation ...................................... 7 DREQ/DACK DMA Mode--Single FIFO Write Operation .. 8 DREQ/DACK DMA Mode--Single FIFO Read Operation . 10 External DMA Mode--FIFO Write, Burst Mode .................. 12 External DMA Mode--FIFO Read, Burst Mode ................... 13 Streaming Mode (JDATA)--FIFO Read/Write ...................... 14 VDATA Mode Timing ............................................................... 15 Raw Pixel Mode Timing ............................................................ 17 JTAG Timing............................................................................... 18 Absolute Maximum Ratings.......................................................... 19 Thermal Resistance .................................................................... 19 ESD Caution................................................................................ 19 Pin Configurations and Function Descriptions ......................... 20 Theory of Operation ...................................................................... 25 Wavelet Engine ........................................................................... 25 Entropy Codecs........................................................................... 25 Embedded Processor System .................................................... 25 Memory System.......................................................................... 25 Internal DMA Engine ................................................................ 25 ADV212 Interface .......................................................................... 26 Video Interface (VDATA Bus).................................................. 26 Host Interface (HDATA Bus) ................................................... 26 Direct and Indirect Registers .................................................... 26 Control Access Registers ........................................................... 27 Pin Configuration and Bus Sizes/Modes ................................ 27 Stage Register .............................................................................. 27 JDATA Mode............................................................................... 27 External DMA Engine ............................................................... 27 Internal Registers............................................................................ 28 Direct Registers........................................................................... 28 Indirect Registers........................................................................ 29 PLL ............................................................................................... 30 Hardware Boot............................................................................ 31 Video Input Formats ...................................................................... 32 Applications..................................................................................... 34 Encode--Multichip Mode......................................................... 34 Decode--Multichip Master/Slave ............................................ 35 Digital Still Camera/Camcorder .............................................. 36 Encode/Decode SDTV Video Application ............................. 37 32-Bit Host Application............................................................. 38 HIPI (Host Interface--Pixel Interface) ................................... 39 JDATA Interface ......................................................................... 40 Outline Dimensions ....................................................................... 41 Ordering Guide .......................................................................... 42 REVISION HISTORY 10/06--Revision 0: Initial Version Rev. 0 | Page 2 of 44 ADV212 The ADV212 can process images at a rate of 40 MSPS in reversible mode and at higher rates when used in irreversible mode. The ADV212 contains a dedicated wavelet transform engine, three entropy codecs, an on-board memory system, and an embedded reduced instruction set computer (RISC) processor that can provide a complete JPEG 2000 compression/decompression solution. The wavelet processor supports the 9/7 irreversible wavelet transform and the 5/3 wavelet transform in reversible and irreversible modes. The entropy codecs support all features in the JPEG 2000 Part 1 specification, except maximum shift region of interest (ROI). The ADV212 operates on a rectangular array of pixel samples called a tile. A tile can contain a complete image, up to the maximum supported size, or some portion of an image. The maximum horizontal tile size supported depends on the wavelet transform selected and the number of samples in the tile. Images larger than the ADV212's maximum tile size can be broken into individual tiles and then sent sequentially to the chip while maintaining a single, fully compliant JPEG 2000 code stream for the entire image. JPEG 2000 FEATURE SUPPORT The ADV212 supports a broad set of features that are included in Part 1 of the JPEG 2000 standard (ISO/IEC 15444). See ADV212 User's Guide for information on the JPEG 2000 features that the ADV212 currently supports. Depending on the particular application requirements, the ADV212 can provide varying levels of JPEG 2000 compression support. It can provide raw code block and attribute data output, which allows the host software to have complete control over the generation of the JPEG 2000 code stream and other aspects of the compression process such as bit-rate control. Otherwise, the ADV212 can create a complete, fully compliant JPEG 2000 code stream (J2C) and enhanced file formats such as JP2. Rev. 0 | Page 3 of 44 ADV212 SPECIFICATONS Specifications apply to IOVDD = 2.5 V or 3.3 V over operating temperature range, unless otherwise specified. SUPPLY VOLTAGES AND CURRENT Table 1. Parameter DC Supply Voltage, Core DC Supply Voltage, Input/Output DC Supply Voltage, Input/Output Input Range Operating Ambient Temperature Range in Free Air Static Current 1 Dynamic Current, Core (JCLK Frequency = 150 MHz) 2 Dynamic Current, Core (JCLK Frequency = 108 MHz) Dynamic Current, Core (JCLK Frequency = 81 MHz) Dynamic Current, Input/Output 1 2 Mnemonic VDD IOVDD IOVDD VIN T IDD Min 1.425 2.375 3.135 -0.3 -40 Typ 1.5 2.5 3.3 +25 15 380 280 210 40 Max 1.575 2.625 3.465 VDDI/O + 0.3 +85 30 440 320 290 50 Unit V V V V C mA mA mA mA mA No clock or input/output activity. ADV212-150 only. INPUT/OUTPUT SPECIFICATIONS Table 2. Parameter High Level Input Voltage High Level Input Voltage Low Level Input Voltage High Level Output Voltage High Level Output Voltage Low Level Output Voltage High Level Input Current Low Level Input Current High Level Three-State Leakage Current Low Level Three-State Leakage Current Input Pin Capacitance Output Pin Capacitance Mnemonic VIH (3.3 V) VIH (2.5 V) VIL (3.3 V, 2.5 V) VOH (3.3 V) VOH (2.5 V) VOL (3.3 V, 2.5 V) IIH IIL IOZH IOZL CI CO Min 2.2 1.9 2.4 2.0 0.4 1.0 1.0 1.0 1.0 8 8 Typ Max Unit V V V V V V A A A A pF pF Test Conditions VDD = maximum VDD = maximum VDD = minimum VDD = minimum, IOH = -0.5 mA VDD = minimum, IOH = -0.5 mA VDD = minimum, IOL = +2 mA VDD = maximum, VIN = VDD VDD = maximum, VIN = 0 V VDD = maximum, VIN = VDD VDD = maximum, VIN = 0V 0.6 Rev. 0 | Page 4 of 44 ADV212 CLOCK AND RESET SPECIFICATIONS Table 3. Parameter MCLK Period MCLK Frequency MCLK Width Low MCLK Width High VCLK Period VCLK Frequency VCLK Width Low VCLK Width High RESET Width Low 1 Mnemonic tMCLK fMCLK tMCLKL tMCLKH tVCLK fVCLK tVCLKL tVCLKH tRESET Min 13.3 10 6 6 13.4 20 5 5 5 Typ Max 100 75.18 50 74.60 Unit ns MHz ns ns ns MHz ns ns MCLK cycles 1 For a definition of MCLK, see Figure 32. tMCLK tMCLKL MCLK tMCLKH tVCLK tVCLKL VCLK tVCLKH 06389-010 Figure 2. Input Clock Rev. 0 | Page 5 of 44 ADV212 NORMAL HOST MODE--WRITE OPERATION Table 4. Parameter WE to ACK, Direct Registers and FIFO Accesses WE to ACK, Indirect Registers Data Setup Data Hold Address Setup Address Hold CS to WE Setup CS Hold Write Inactive Pulse Width (Minimum Time Until Next WE Pulse) Write Active Pulse Width Write Cycle Time 1 Mnemonic tACK (direct) tACK (indirect) tSD tHD tSA tHA tSC tHC tWH tWL tWCYC Min 5 5 3.0 1.5 2 2 0 0 2.5 JCLK 1 2.5 JCLK 5 JCLK Typ Max 1.5 x JCLK + 7.0 2.5 x JCLK + 7.0 Unit ns ns ns ns ns ns ns ns ns ns ns For a definition of JCLK, see Figure 32. tSA ADDR tHA tSC CS tHC tWCYC tWL WE tWH tACK ACK tHD 06389-012 tSD HDATA VALID Figure 3. Normal Host Mode--Write Operation Rev. 0 | Page 6 of 44 ADV212 NORMAL HOST MODE--READ OPERATION Table 5. Parameter RD to ACK, Direct Registers and FIFO Accesses RD to ACK, Indirect Registers Read Access Time, Direct Registers Read Access Time, Indirect Registers Data Hold CS to RD Setup Address Setup CS Hold Address Hold Read Inactive Pulse Width Read Active Pulse Width Read Cycle Time, Direct Registers 1 Mnemonic tACK (direct) 1 tACK (indirect)1 tDRD (direct) tDRD (indirect) tHZRD tSC tSA tHC tHA tRH tRL tRCYC Min 5 10.5 x JCLK 5 10.5 x JCLK 2 0 2 0 2 2.5 JCLK 2 2.5 JCLK 5.0 JCLK Typ Max 1.5 x JCLK + 7.0 15.5 x JCLK + 7.0 1.5 x JCLK + 7.0 15.5 x JCLK + 7.0 8.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns Timing relationship between ACK falling transition and HDATA valid is not guaranteed. HDATA valid hold time is guaranteed with respect to RD rising transition. A minimum of three JCLK cycles is recommended between ACK assert and RD deassert. 2 For a definition of JCLK, see Figure 32. tSA ADDR tHA tSC CS tHC tRCYC tRL RD tRH tACK ACK 06389-011 tDRD HDATA VALID tHZRD Figure 4. Normal Host Mode--Read Operation Rev. 0 | Page 7 of 44 ADV212 DREQ/DACK DMA MODE--SINGLE FIFO WRITE OPERATION Table 6. Parameter DREQ Pulse Width DACK Assert to Subsequent DREQ Delay WE to DACK Setup Data to DACK Deassert Setup Data to DACK Deassert Hold DACK Assert Pulse Width DACK Deassert Pulse Width WE Hold After DACK Deassert WE Assert to FSRQ Deassert (FIFO Full) DACK to DREQ Deassert (DR x PULS = 0) 1 Mnemonic DREQPULSE tDREQ tWESU tSU tHD DACKLO DACKHI tWEHD WFSRQ tDREQRTN Min 1 JCLK 1 2.5 JCLK 0 2 2 2 JCLK 2 JCLK 0 1.5 JCLK 2.5 JCLK Typ Max 15 JCLK 3.5 x JCLK + 8.5 Unit ns ns ns ns ns ns ns ns 2.5 x JCLK + 7.5 3.5 x JCLK + 9.0 ns ns For a definition of JCLK, see Figure 32. DREQ PULSE tDREQ DREQ DACK HI DACK LO DACK tWESU WE tWEHD tHD HDATA 0 1 2 3 Figure 5. Single Write for DREQ/DACK DMA Mode for Assigned DMA Channel (EDMOD0/EDMOD1 <14:11> Not Programmed to a Value of 0000) tDREQRTN DREQ DACK HI DACK LO DACK tWESU WE tWEHD tHD HDATA 0 1 2 Figure 6. Single Write for DREQ/DACK DMA Mode for Assigned DMA Channel (EDMOD0/EDMOD1 <14:11> Programmed to a Value of 0000) Rev. 0 | Page 8 of 44 06389-014 tSU 06389-013 tSU ADV212 DREQPULSE tDREQ DREQ DACK HI DACK LO DACK tWESU WEFB tWEHD tHD HDATA 0 1 2 Figure 7. Single Write Cycle for Fly-By DMA Mode (DREQ Pulse Width Is Programmable) FCS0 RD WFSRQ FSRQ0 FIFO NOT FULL FIFO FULL HDATA 0 1 2 NOT WRITTEN TO FIFO 06389-021 tSU tHD Figure 8. Single Write Access for DCS DMA Mode Rev. 0 | Page 9 of 44 06389-015 tSU ADV212 DREQ/DACK DMA MODE--SINGLE FIFO READ OPERATION Table 7. Parameter DREQ Pulse Width DACK Assert to Subsequent DREQ Delay RD to DACK Setup DACK to Data Valid Data Hold DACK Assert Pulse Width DACK Deassert Pulse Width RD Hold after DACK Deassert RD Assert to FSRQ Deassert (FIFO Empty) DACK to DREQ Deassert (DR x PULS = 0) 1 Mnemonic DREQPULSE tDREQ tRDSU tRD tHD DACKLO DACKHI tRDHD RDFSRQ tDREQRTN Min 1 JCLK 1 2.5 JCLK 0 2.5 1.5 2 JCLK 2 JCLK 0 1.5 JCLK 2.5 JCLK Typ Max 15 JCLK 3.5 x JCLK + 9.0 11 Unit ns ns ns ns ns ns ns ns 2.5 x JCLK + 9.0 3.5 x JCLK + 9.0 ns ns For a definition of JCLK, see Figure 32. DREQPULSE tDREQ DREQ DACK HI DACK LO DACK tRDSU RD tRDHD HDATA 0 1 2 Figure 9. Single Read for DREQ/DACK DMA Mode for Assigned DMA Channel (EDMOD0/EDMOD1 <14:11> Not Programmed to a Value of 0000) tDREQRTN DREQ DACK HI DACK LO DACK tRDSU RD tRDHD HDATA 0 1 2 Figure 10. Single Read for DREQ/DACK DMA Mode for Assigned DMA Channel (EDMOD0/EDMOD1 <14:11> Programmed to a Value of 0000) Rev. 0 | Page 10 of 44 06389-019 tRD tHD 06389-018 tRD tHD ADV212 DREQPULSE tDREQ DREQ DACK HI DACK LO DACK tRDSU RDFB tRDHD HDATA 0 1 2 Figure 11. Single Read Cycle for Fly-By DMA Mode (DREQ Pulse Width Is Programmable) FCS0 RD RDFSRQ FIFO NOT EMPTY FSRQ0 FIFO EMPTY tRD HDATA 0 tHD 1 06389-090 Figure 12. Single Read Access for DCS DMA Mode Rev. 0 | Page 11 of 44 06389-020 tRD tHD ADV212 EXTERNAL DMA MODE--FIFO WRITE, BURST MODE Table 8. Parameter DREQ Pulse Width 1 WE to DREQ Deassert (DR x PULS = 0) DACK to WE Setup Data Setup Data Hold WE Assert Pulse Width WE Deassert Pulse Width WEDeassert to Next DREQ WE Deassert to DACK Deassert 1 2 Mnemonic DREQPULSE tDREQRTN tDACKSU tSU tHD WELO WEHI tDREQWAIT tWE_DACK Min 1 JCLK 2 2.5 JCLK 0 2.5 2 1.5 JCLK 1.5 JCLK 2.5 JCLK 0 Typ Max 15 JCLK 3.5 x JCLK + 7.5 Unit ns ns ns ns ns ns ns ns ns 4.5 x JCLK + 9.0 Applies to assigned DMA channel, if EDMOD0 or EDMOD1 <14:11> is programmed to a nonzero value. For a definition of JCLK, see Figure 32. DREQPULSE tDREQWAIT DREQ tWE_DACK DACK tDACKSU WE WELO WEHI tHD HDATA 14 15 06389-022 tSU 0 1 13 Figure 13. Burst Write Cycle for DREQ/DMA Mode for Assigned DMA Channel (EDMOD0/EDMOD1 <14:11> Not Programmed to a Value of 0000) tDREQRTN DREQ tDREQWAIT tWE_DACK DACK tDACKSU WE WELO WEHI tHD 06389-023 tSU HDATA 0 1 13 14 15 Figure 14. Burst Write Cycle for DREQ/DMA Mode for Assigned DMA Channel (EDMOD0/EDMOD1 <14:11> Programmed to a Value of 0000) tDREQRTN DREQ DACK tDREQWAIT tWE_DACK tDACKSU WEFB WELO WEHI tHD 06389-024 tSU HDATA 0 1 13 14 15 Figure 15. Burst Write Cycle for Fly-By DMA Mode Rev. 0 | Page 12 of 44 ADV212 EXTERNAL DMA MODE--FIFO READ, BURST MODE Table 9. Parameter DREQ Pulse Width 1 RD to DREQ Deassert (DR x PULS = 0) DACK to RD Setup RD to Data Valid Data Hold RD Assert Pulse Width RD Deassert Pulse Width RD Deassert to Next DREQ RD Deassert to DACK Deassert 1 2 Mnemonic DREQPULSE tDREQRTN tDACKSU tRD tHD RDLO RDHI tDREQWAIT tRD_DACK Min 1 JCLK 2 2.5 JCLK 0 2.5 2.5 1.5 JCLK 1.5 JCLK 2.5 JCLK 0 Typ Max 15 JCLK 3.5 x JCLK + 7.5 Unit ns ns ns 9.7 ns ns ns ns ns ns 3.5 x JCLK + 7.5 Applies to assigned DMA channel if EDMOD0 or EDMOD1 <14:11> is programmed to a nonzero value. For a definition of JCLK, see Figure 32. tDREQPULSE DREQ tDREQWAIT tRD_DACK DACK tDACKSU RD RDLO RDHI tHD HDATA 0 1 13 14 15 06389-025 tRD Figure 16. Burst Read Cycle for DREQ/DACK DMA Mode for Assigned DMA Channel (EMOD0/EDMOD1 <14:11> Not Programmed to a Value of 0 tDREQWAIT DREQ DACK tDREQRTN tDACKSU RDLO tRD_DACK RDHI RD tHD 06389-026 HDATA 0 1 13 14 15 tRD Figure 17. Burst Read Cycle for DREQ/DACK DMA Mode for Assigned DMA Channel (EMOD0/EDMOD1 <14:11> Programmed to a Value of 0000) tDREQRTN DREQ tDREQWAIT tRD_DACK DACK tDACKSU RDFB tHD HDATA 0 1 13 14 15 06389-027 tRD RD Figure 18. Burst Read Cycle for Fly-By DMA Mode Rev. 0 | Page 13 of 44 ADV212 STREAMING MODE (JDATA)--FIFO READ/WRITE Table 10. Parameter MCLK to JDATA Valid MCLK to VALID Assert/Deassert HOLD Setup to Rising MCLK HOLD Hold from Rising MCLK JDATA Setup to Rising MCLK JDATA Hold from Rising MCLK 1 Mnemonic JDATATD VALIDTD HOLDSU HOLDHD JDATASU JDATAHD Min 1.5 JCLK 1 1.5 JCLK 3 3 3 3 Typ Max 2.5 x JCLK + 9.5 2.5 x JCLK + 8.0 Unit ns ns ns ns ns ns For a definition of JCLK, see Figure 32. MCLK JDATATD JDATA JDATASU JDATAHD VALIDTD VALID HOLD Figure 19. Streaming Mode Timing--Encode Mode JDATA Output MCLK JDATAHD JDATASU JDATA VALIDTD VALID HOLDHD HOLDSU HOLD 06389-029 Figure 20. Streaming Mode Timing--Decode Mode JDATA Input Rev. 0 | Page 14 of 44 06389-028 HOLDSU HOLDHD ADV212 VDATA MODE TIMING Table 11. Parameter VCLK to VDATA Valid Delay (VDATA Output) VDATA Setup to Rising VCLK (VDATA Input) VDATA Hold from Rising VCLK (VDATA Input) HSYNC Setup to Rising VCLK HSYNC Hold from Rising VCLK VCLK to HSYNC Valid Delay VSYNC Setup to Rising VCLK VSYNC Hold from Rising VCLK VCLK to VSYNC Valid Delay FIELD Setup to Rising VCLK FIELD Hold from Rising VCLK VCLK to FIELD Valid Decode Slave Data Sync Delay (HSYNC Low to First 0xFF of EAV/SAV Code) Decode Slave Data Sync Delay (HSYNC Low to First Data for HVF Mode) 1 Mnemonic VDATATD VDATASU VDATAHD HSYNCSU HSYNCHD HSYNCTD VSYNCSU VSYNCHD VSYNCTD FIELDSU FIELDHD FIELDTD SYNC DELAY Min 4 4 3 4 Typ Max 12 12 3 4 12 4 3 12 81 101 Unit ns ns ns ns ns ns ns ns ns ns ns VCLK cycles VCLK cycles The sync delay value varies according to the application. Refer to the ADV212 User Guide for more information. VCLK VDATASU VDATAHD VDATA (IN) Cr Y Cb Y FF 00 00 EAV FF 00 00 SAV Cb Y Cr 06389-091 Figure 21. Encode Video Mode Timing--CCIR 656 Mode VCLK HSYNC HSYNCSU HSYNCHD 06389-092 VDATA (IN) Cb Y Cr Y Cb Y Cr Y Figure 22. Encode Video Mode Timing--HVF Mode (HSYNC Timing) (HSYNC Programmed for Negative Polarity) VCLK VSYNCSU VSYNCHD VSYNC FIELDSU FIELD Figure 23. Encode Video Mode Timing--HVF Mode (VSYNC and FIELD Timing) (VSYNC and FIELD Programmed for Negative Polarity) Rev. 0 | Page 15 of 44 06389-093 FIELDHD ADV212 VCLK VDATATD VDATA (OUT) HSYNCSU HSYNC (IN) FF 00 00 EAV HSYNCHD Cb Y VSYNCHD VSYNCSU SYNC DELAY VSYNC (IN) 06389-094 FIELDSU FIELD (IN) Figure 24. Decode Video Mode Timing--CCIR 656 Mode, Decode Slave (HSYNC, VSYNC, and FIELD Programmed to Negative Polarity) VCLK VDATATD VDATA (OUT) HSYNCSU HSYNC (IN) VSYNCHD VSYNCSU VSYNC (IN) SYNC DELAY Cb Y Cr Y HSYNCHD Cb Y FIELD (IN) Figure 25. Decode Video Mode Timing--HVF Mode, Decode Slave (HSYNC, VSYNC, and FIELD Programmed to Negative Polarity) VCLK VDATATD VDATA (OUT) Cb HSYNCTD HSYNC (OUT) VSYNCTD VSYNC (OUT) FIELDTD FIELD (OUT) 06389-096 FF 00 00 SAV Cb Y Cr Figure 26. Decode Video Mode Timing--CCIR 656 Mode, Decode Master (HSYNC, VSYNC, and FIELD Programmed to Negative Polarity) VCLK VDATATD VDATA (OUT) Cb Y Cr Y Cb Y Cb Y Cr HSYNC (OUT) VSYNCTD VSYNC (OUT) 06389-097 FIELDTD FIELD (OUT) Figure 27. Decode Video Mode Timing--HVF Mode, Decode Master (HSYNC, VSYNC, and FIELD Programmed to Negative Polarity) Rev. 0 | Page 16 of 44 06389-095 FIELDSU ADV212 RAW PIXEL MODE TIMING Table 12. Parameter VCLK to PIXELDATA Valid Delay (PIXELDATA Output) PIXELDATA Setup to Rising VCLK (PIXELDATA Input) PIXELDATA Hold from Rising VCLK (PIXELDATA Input) VCLK to VRDY Valid Delay VFRM Setup to Rising VCLK (VFRAME Input) VFRM Hold from Rising VCLK (VFRAME Input) VCLK to VFRM Valid Delay (VFRAME Output) VSTRB Setup to Rising VCLK VSTRB Hold from Rising VCLK Mnemonic VDATATD VDATASU VDATAHD VRDYTD VFRMSU VFRMHD VFRMTD VSTRBSU VSTRBHD Min 4 4 12 3 4 12 4 3 Typ Max 12 Unit ns ns ns ns ns ns ns ns ns VCLK VDATASU VDATAHD PIXEL DATA (IN) VFRMSU VFRM (IN) VRDY TD VRDY (OUT) VSTRBSU VSTRB (IN) PIXEL 1 PIXEL 2 PIXEL 3 VFRMHD VSTRBHD RAW PIXEL MODE--ENCODE VCLK VDATATD PIXELDATA (OUT) PIXEL 1 PIXEL 2 PIXEL 3 VFRMTD VFRM (OUT) VRDY TD VRDY (OUT) VSTRBHD VSTRBSU 06389-031 VSTRB (IN) RAW PIXEL MODE--DECODE Figure 28. Raw Pixel Modes Rev. 0 | Page 17 of 44 ADV212 JTAG TIMING Table 13. Parameter TCK Period TDI or TMS Setup Time TDI or TMS Hold Time TDO Hold Time TDO Valid TRST Hold Time TRST Setup Time TRST Pulse Width Low Mnemonic TCK TDISU TDIHD TDOHD TDOVALID TRSTHD TRSTSU TRSTLO Min 134 4.0 4.0 0.0 4.0 4.0 4 Typ Max Unit ns ns ns ns ns ns ns TCK cycles 10.0 TCK TDOVALID TDOHD TDO TDISU TDI TDIHD TMS TRSTHD TRST 06389-032 TRSTSU Figure 29. JTAG Timing Rev. 0 | Page 18 of 44 ADV212 ABSOLUTE MAXIMUM RATINGS Table 14. Parameter VDD - Supply Voltage, Core IOVDD - Supply Voltage, Input/Output Storage Temperature [TS] Reflow Soldering Pb-Free, 121-Ball Pb-Free, 144-Ball Rating -0.3 V to +1.65 V -0.3 V to 3.63 V -65C to +150C 260C [20 sec to 40 sec] 260C [20 sec to 40 sec] THERMAL RESISTANCE JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 15. Thermal Resistance Package Type 144-Ball ADV212BBCZ 121-Ball ADV212BBCZ JA 22.5 32.8 JC 3.8 7.92 Unit C/W C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. 0 | Page 19 of 44 ADV212 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L 06389-035 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M BOTTOM VIEW (Not to Scale) BOTTOM VIEW (Not to Scale) Figure 30.121-Ball Pin Configuration Figure 31. 144-Ball Pin Configuration Rev. 0 | Page 20 of 44 06389-036 ADV212 Table 16. Pin Function Descriptions 121-Ball Package Pin No. 119 117 Location L9 L7 144-Ball Package Pin No. 132 131 Location L12 L11 Mnemonic MCLK RESET Pins Used 1 1 Type I I Description System Input Clock. See the PLL section. Reset. Causes the ADV212 to immediately reset. CS, RD, WE, DACK0, DACK1, DREQ0, and DREQ1 must be held high when a RESET is applied. Host Data Bus. With HDATA [23:16], HDATA [27:24], and HDATA [31:28], these pins make up the 32-bit wide host data bus. The async host interface is interfaced together with ADDR[3:0], CS, WE, RD, and ACK. Unused HDATA pins should be pulled down via a 10 k resistor. Address Bus for the Host Interface. Chip Select. This signal is used to qualify addressed read and write access to the ADV212 using the host interface. Write Enable Used with the Host Interface. Read Enable When Fly-By DMA Is Enabled. Simultaneous assertion of WE and DACK low activates the HDATA bus, even if the DMA channels are disabled. Read Enable Used with the Host Interface. Write Enable When Fly-By DMA Is Enabled. Simultaneous assertion of RD and DACK low activates the HDATA bus, even if the DMA channels are disabled. Acknowledge. Used for direct register accesses. This signal indicates that the last register access was successful. Due to synchronization issues, control and status register accesses might incur an additional delay; therefore, the host software should wait for acknowledgment from the ADV212 before attempting another register access. Accesses to the FIFOs (external DMA modes), on the other hand, are guaranteed to occur immediately, provided that space is available; therefore, the host software does not need to wait for ACK before attempting another register access, provided that the timing constraints are observed. If ACK is shared with more than one device, ACK should be connected to a pull-up resistor (10 k) and the PLL_HI register, Bit 4, must be set to 1. Interrupt. This pin indicates that the ADV212 requires the attention of the host processor. This pin can be programmed to indicate the status of the internal interrupt conditions within the ADV212. The interrupt sources are enabled via the bits in register EIRQIE. 37 to 34, 27 to 25, 16, 15, 24, 14 to 12, 2, 6, 5 D4 to D1, C5 to C3, B5, B4, C2, B3 to B1, A2, A6, A5 64, 49 to 51, 37 to 39, 25 to 27, 13 to 15, 2 to 4 F4, E1 to E3, D1 to D3, C1 to C3, B1 to B3, A2 to A4 HDATA [15:0] 16 I/O 88, 107, 87, 97 96 H11, K8, H10, J9 J8 108 to 106, 96 95 J12, J11, J10, H12 H11 ADDR [3:0] CS 4 1 I I 95 J7 94 H10 WE 1 RDFB 2 1 I 86 H9 84 G12 RD1 WEFB 3 1 I 85 H8 83 G11 ACK 1 O 76 G10 82 G10 IRQ 1 O Rev. 0 | Page 21 of 44 ADV212 121-Ball Package Pin No. 63 Location F8 144-Ball Package Pin No. 72 Location F12 Mnemonic DREQ0 Pins Used 1 Type O Description Data Request for External DMA Interface. Indicates that the ADV212 is ready to send/receive data to/from the FIFO assigned to DMA Channel 0. FIFO Service Request. Used in DCS-DMA Mode. Service request from the FIFO assigned to Channel 0 (asynchronous mode). Valid Indication for JDATA Input/Output Stream. Polarity of this pin is programmable in the EDMOD0 register. VALID is always an output. Boot Mode Configuration. This pin is read on reset to determine the boot configuration of the on-board processor. The pin should be tied to IOVDD or DGND through a 10 k resistor. Data Acknowledge for External DMA Interface. Signal from the host CPU, which indicates that the data transfer request (DREQ0) has been acknowledged and that the data transfer can proceed. This pin must be held high at all times if the DMA interface is not used, even if the DMA channels are disabled. External Hold Indication for JDATA Input/Output Stream. Polarity is programmable in the EDMOD0 register. This pin is always an input. FIFO Chip Select. Used in DCS-DMA Mode. Chip select for the FIFO assigned to Channel 0 (asynchronous mode). Data Request for External DMA Interface. Indicates that the ADV212 is ready to send/receive data to/from the FIFO assigned to DMA Channel 1. FIFO Service Request. Used in DCS-DMA Mode. Service request from the FIFO assigned to Channel 1 (asynchronous mode). Boot Mode Configuration. This pin is read on reset to determine the boot configuration of the on-board processor. The pin should be tied to IOVDD or DGND through a 10 k resistor. Data Acknowledge for External DMA Interface. Signal from the host CPU, which indicates that the data transfer request (DREQ1) has been acknowledged and data transfer can proceed. This pin must be held high at all times unless a DMA or JDATA access is occurring. This pin must be held high at all times if the DMA interface is not used, even if the DMA channels are disabled. FIFO Chip Select. Used in DCS-DMA Mode. Chip select for the FIFO assigned to Channel 1 (asynchronous mode). Host Expansion Bus. JDATA Bus (JDATA Mode). Host Expansion Bus. JDATA Bus (JDATA Mode). FSRQ0 O VALID O CFG1 I 64 F9 71 F11 DACK0 1 I HOLD I FCS0 I 65 F10 70 F10 DREQ1 1 O FSRQ1 O CFG2 I 75 G9 69 F9 DACK1 1 I FCS1 I 90 to 92, 78 J2 to J4, H1 111,97 to 99 K3, J1 to J3 79 to 81, 70 H2 to H4, G4 100, 85 to 87 J4, H1 to H3 HDATA [31:28] JDATA [7:4] HDATA [27:24] JDATA [3:0] 4 I/O I/O I/O I/O 4 Rev. 0 | Page 22 of 44 ADV212 121-Ball Package Pin No. 69, 68, 59, 58 57, 46 to 48 Location G3, G2, F4, F3 F2, E2, E3, E4 144-Ball Package Pin No. 88,73 to 75 76, 61 to 63 Location H4, G1 to G3 G4, F1 to F3 Mnemonic HDATA [23:20] HDATA [19:16] VDATA [15:12] SCOMM7 SCOMM6 SCOMM5 Pins Used 4 4 Type I/O I/O I/O Description Host Expansion Bus. Host Expansion Bus. Video Data. Only used for raw pixel video mode. Unused pins should be pulled down via a 10 k resistor. Serial Communication. For internal use only. This pin should be tied low via a 10 k resistor. Serial Communication. For internal use only. This pin should be tied low via a 10 k resistor. Serial Communication. This pin must be used in multiple chip mode to align the outputs of two or more ADV212s. For details, see the Applications section and the AN-796 Application Note. When not used, this pin should be tied low via a 10 k resistor. LCODE Output in Encode Mode. When LCODE is enabled, the output on this pin indicates on a high transition that the last data-word for a field has been read from the FIFO. For an 8-bit interface, such as JDATA, LCODE is asserted for four consecutive bytes and is enabled by default. Serial Communication. For internal use only. This pin should be tied low via a 10 k resistor. Serial Communication. For internal use only. This pin should be tied low via a 10 k resistor. Serial Communication. For internal use only. This pin should be tied low via a 10 k resistor. Serial Communication. This pin should be tied low via a10 k resistor. Video Data Clock. This pin must be supplied if video data is input/output on the VDATA bus. Video Data. Unused pins should be pulled down via a 10 k resistor. 112 113 114 L2 L3 L4 134 135 136 M2 M3 M4 8 I/O I/O I/O 100 K1 121 L1 SCOMM4 O 101 115 103 102 53 44, 43, 29, 31, 32, 18 to 20, 22, 21, 7, 10 41 K2 L5 K4 K3 E9 D11, D10, C7, C9, C10, B7, B8, B9, B11, B10, A7, A10 D8 122 123 109 110 60 46 to 48, 34 to 36, 22 to 24, 9 to 11 58 L2 L3 K1 K2 E12 D10 to D12, C10 to C12, B10 to B12, A9 to A11 E10 SCOMM3 SCOMM2 SCOMM1 SCOMM0 VCLK VDATA [11:0] 1 12 I O I O I I/O VSYNC VFRM 1 I/O 42 54 94 108 D9 E10 J6 K9 59 57 120 119 E11 E9 K12 K11 HSYNC VRDY FIELD VSTRB TCK TRS 1 1 1 1 I/O O I/O I I I Vertical Sync for Video Mode. Raw Pixel Mode Framing Signal. When this pin is asserted high, it indicates the first sample of a tile. Horizontal Sync for Video Mode. Raw Pixel Mode Ready Signal. Field Sync for Video Mode. Raw Pixel Mode Transfer Strobe. JTAG Clock. If not used, this pin should be connected to ground via a pull-down resistor. JTAG Reset. If the JTAG is used, this pin must be toggled low to high. If JTAG is not used, this pin must be held low. Rev. 0 | Page 23 of 44 ADV212 121-Ball Package Pin No. 98 Location J10 144-Ball Package Pin No. 118 Location K10 Mnemonic TMS Pins Used 1 Type I Description JTAG Mode Select. If JTAG is used, connect 10 k pull-up resistor to this pin. If not used, this pin should be connected to ground via a pull-down resistor. JTAG Serial Data Input. If JTAG is used, connect a 10 k pull-up resistor to this pin. If JTAG is not used, this pin should be connected to ground via a pull-down resistor. JTAG Serial Data Output. If this pin is not used, do not connect it. Positive Supply for Core. 116 L6 141 M9 TDI 1 I 109 3, 8, 40, 84, 120 K10 A3, A8, D7, H7, L10 130 18, 19, 30, 31, 42, 43, 102, 103, 114, 115, 126, 127, 142 1, 5 to 8, 12, 17, 20, 29, 32, 41, 44, 52 to 56, 65 to 68, 77 to 81, 89 to 93, 101, 104, 105, 113, 116, 125, 128, 133, 137 to 140, 143, 144 16, 21, 28, 33, 40, 45, 112, 117, 124, 129 L10 B6, B7, C6, C7, D6, D7, J6, J7, K6, K7, L6, L7, M10 A1, A5 to A8, A12, B5, B8, C5, C8, D5, D8, E4 to E8, F5 to F8, G5 to G9, H5 to H9, J5, J8, J9, K5, K8, L5, L8, M1, M5 to M8, M11, M12 B4, B9, C4, C9, D4, D9, K4, K9, L4, L9 TDO VDD 1 O V 1, 4, 9,11, 23, 33, 39, 45, 49 to 51, 55, 56, 60 to 62, 66, 67, 71 to 73, 77, 83, 89,99, 110, 111, 118, 121 A1, A4, A9, A11, C1, C11, D6, E1, E5 to E7, E11, F1, F5 to F7, F11, G1, G5 to G7, G11, H6, J1, J11, K11, L1, L8, L11 DGND GND Ground. 17, 28, 30, 38, 52, 74, 82, 93, 104 to 106 1 B6, C6, C8, D5, E8, G8, H5, J5, K5 to K7 IOVDD V Positive Supply for Input/Output. In fly-by mode DMA, the function of the RD and WE signals (for DMA only) are reversed. This allows a host to move data between an external device and the ADV212 with the use of a single strobe. 2 In encode mode with fly-by DMA, the host can use the RDFB signal (WE pin) to simultaneously read from the ADV212 and write to an external device like memory. 3 In decode mode with fly-by DMA, the host can use the WEFB signal (RD pin) to simultaneously read from the external device and write to the ADV212. Rev. 0 | Page 24 of 44 ADV212 THEORY OF OPERATION The input video or pixel data is passed on to the ADV212's pixel interface, and samples are deinterleaved and passed on to the wavelet engine, which decomposes each tile or frame into subbands using the 5/3 or 9/7 filters. The resultant wavelet coefficients are then written to the internal memory. The entropy codecs code the image data so that it conforms to the JPEG 2000 standard. An internal DMA provides high bandwidth memory-to-memory transfers, as well as high performance transfers between functional blocks and memory. ENTROPY CODECS The entropy codec block performs context modeling and arithmetic coding on a code block of the wavelet coefficients. Additionally, this block also performs the distortion metric calculations during compression that are required for optimal rate and distortion performance. Because the entropy coding process is the most computationally intensive operation in the JPEG 2000 compression process, three dedicated hardware entropy codecs are provided on the ADV212. WAVELET ENGINE The ADV212 provides a dedicated wavelet transform processor based on the Analog Devices proven and patented SURF technology. This processor can perform up to six wavelet decomposition levels on a tile. In encode mode, the wavelet transform processor takes in uncompressed samples, performs the wavelet transform and quantization, and writes the wavelet coefficients in all frequency subbands to the internal memory. Each of these subbands is further broken down into code blocks. The code-block dimensions can be user defined and are used by the wavelet transform processor to organize the wavelet coefficients into code blocks when writing to the internal memory. Each completed code block is then entropy coded by one of the entropy codecs. In decode mode, wavelet coefficients are read from internal memory and recomposed into uncompressed samples. EMBEDDED PROCESSOR SYSTEM The ADV212 incorporates an embedded 32-bit RISC processor. This processor is used for configuration, control, and management of the dedicated hardware functions, as well as for parsing and generation of the JPEG 2000 code stream. The processor system includes memory for both the program and data memory, the interrupt controller, the standard bus interfaces, and other hardware functions such as timers and counters. MEMORY SYSTEM The main function of the memory system is to manage wavelet coefficient data, interim code-block attribute data, and temporary workspace for creating, parsing, and storing the JPEG 2000 code stream. The memory system can also be used for the program and data memory for the embedded processor. INTERNAL DMA ENGINE The internal DMA engine provides high bandwidth memoryto-memory transfers, as well as high performance transfers between memory and functional blocks. This function is critical for high speed generation and parsing of the code stream. Rev. 0 | Page 25 of 44 ADV212 ADV212 INTERFACE There are several possible modes to interface to the ADV212 using the VDATA bus and the HDATA bus or the HDATA bus alone. The control and data channel bus widths can be specified independently, which allows the ADV212 to support applications that require control and data buses of different widths. The host interface is used for configuration, control, and status functions, as well as for transferring compressed data streams. It can be used for uncompressed data transfers in certain modes. The host interface can be shared by as many as three concurrent data streams in addition to control and status communications. The data streams are * * * Uncompressed tile data (for example, still image data) Fully encoded JPEG 2000 code stream (or unpackaged code blocks) Code-block attributes VIDEO INTERFACE (VDATA BUS) The video interface can be used in applications in which uncompressed pixel data is on a separate bus from compressed data. For example, it is possible to use the VDATA bus to input uncompressed video while using the HDATA bus to output the compressed data. This interface is ideal for applications requiring very high throughput, such as live video capture. Optionally, the ADV212 interlaces ITU-R BT.656 resolution video on the fly prior to wavelet processing, which yields significantly better compression performance for temporally coherent frame-based video sources. Additionally, high definition digital video such as SMPTE 274M (1080i) is supported using two or more ADV212 devices. The video interface can support video data or still image data input/output in 8-/10-/12-bit formats, in YCbCr format, or in single input mode. YCbCr data must be in 4:2:2 format. Video data can be input/output in several different modes on the VDATA bus, as described in Table 17. In all these modes, the pixel clock must be input on the VCLK pin. Table 17. Video Input/Output Modes Mode EAV/SAV HVF Description Accepts video with embedded EAV/SAV codes, where the YCbCr data is interleaved onto a single bus. Accepts video data accompanied with separate H, V, and F signals, where YCbCr data is interleaved onto a single bus. Used for still picture data and nonstandard video. VFRM, VSTRB, and VRDY are used to program the dimensions of the image. The ADV212 uses big endian byte alignment for 16- and 32-bit transfers. All data is left-justified (MSB). Pixel Input on the Host Interface Pixel input on the host interface supports 8-/10-/12-/14-/16-bit raw pixel data formats. It can be used for pixel (still image) input/output or compressed video output. Because there are no timing codes or sync signals associated with the input data on the host interface, dimension registers and internal counters are used and must be programmed to indicate the start and end of the frame. Refer to the ADV202 in HIPI Mode technical note for information about using the ADV212 in this mode. Host Bus Configuration For maximum flexibility, the host interface provides several configurations to meet particular system requirements. The default bus mode uses the same pins to transfer control, status, and data to and from the ADV212. In this mode, the ADV212 can support 16- and 32-bit control transfers and 8-/16-/32-bit data transfers. The size of these buses can be selected independently, allowing, for example, a 16-bit microcontroller to configure and control the ADV212 while still providing 32-bit data transfers to an ASIC or external memory system. Raw Video HOST INTERFACE (HDATA BUS) The ADV212 can connect directly to a wide variety of host processors and ASICs using an asynchronous SRAM-style interface, DMA accesses, or streaming mode (JDATA) interface. The ADV212 supports 16- and 32-bit buses for control and 8-/16-/32-bit buses for data transfer. DIRECT AND INDIRECT REGISTERS To minimize pin count and cost, the number of address pins is limited to four, which yields a total direct address space of 16 locations. These locations are most commonly used by the external controller and are, therefore, accessible directly. All other registers in the ADV212 can be accessed indirectly through the IADDR and IDATA registers. Rev. 0 | Page 26 of 44 ADV212 CONTROL ACCESS REGISTERS With the exception of the indirect address and data registers (IADDR and IDATA), all control/status registers in the ADV212 are 16 bits wide and are half-word (16-bit) addressable only. When 32-bit host mode is enabled, the upper 16 bits of the HDATA bus are ignored on writes and return all zeros on reads of 16-bit registers. has been provided to allow 16-bit hosts to access these registers and memory locations using the stage register (STAGE). STAGE is accessed as a 16-bit register using HDATA [15:0]. Prior to writing to the desired register, the stage register must be written with the upper (most significant) half-word. When the host subsequently writes the lower half-word to the desired control register, HDATA is combined with the previously staged value to create the required 32-bit value that is written. When a register is read, the upper (most significant) half-word is returned immediately on HDATA and the lower half-word can be retrieved by reading the stage register on a subsequent access. For details on using the stage register, see the ADV212 User's Guide. Note that the stage register does not apply to the three data channels (PIXEL, CODE, ATTR). These channels are always accessed at the specified data width and do not require the use of the stage register. PIN CONFIGURATION AND BUS SIZES/MODES The ADV212 provides a wide variety of control and data configurations, which allows it to be used in many applications with little or no glue logic. The modes described in this section are configured using the BUSMODE register. In this section, host refers to normal addressed accesses (CS/RD/WE/ADDR) and data refers to external DMA accesses (DREQ/DACK). 32-Bit Host/32-Bit Data In this mode, the HDATA<31:0> pins provide full 32-bit wide data access to PIXEL, CODE, ATTR FIFOs. JDATA MODE JDATA mode is typically used only when the dedicated video interface (VDATA) is also enabled. This mode allows code stream data (compressed data compliant with JPEG 2000) to be input or output on a single dedicated 8-bit bus (JDATA<7:0>). The bus is always an output during compression operations, and is an input during decompression. A 2-pin handshake is used to transfer data over this synchronous interface. VALID is used to indicate that the ADV212 is ready to provide or accept data and is always an output. HOLD is always an input and is asserted by the host if it cannot accept/provide data. For example, JDATA mode allows real-time applications, in which pixel data is input over the VDATA bus while the compressed data stream is output over the JDATA bus. 16-Bit Host/32-Bit Data This mode allows a 16-bit host to configure and communicate with the ADV212 while allowing 32-bit accesses to the PIXEL, CODE, ATTR FIFOs using the external DMA capability. All addressed host accesses are 16 bits and, therefore, use only the HDATA<15:0> pins. The HDATA<31:16> pins provide the additional 16 bits necessary to support the 32-bit external DMA transfers to and from the FIFOs only. 16-Bit Host/16-Bit Data This mode uses 16-bit transfers if used for host or external DMA data transfers. 16-Bit Host/8-Bit Data (JDATA Bus Mode) This mode provides separate data input/output and host control interface pins. Host control accesses are 16 bits and use HDATA<15:0>, whereas the dedicated data bus uses JDATA<7:0>. JDATA uses a valid/hold synchronous transfer protocol. The direction of the JDATA bus is determined by the mode of the ADV212. If the ADV212 is encoding (compression), JDATA<7:0> is an output. If the ADV212 is decoding (decompression), JDATA<7:0> is an input. Host control accesses remain asynchronous. See also JDATA section below. EXTERNAL DMA ENGINE The external DMA interface is provided to enable high bandwidth data input/output between an external DMA controller and the ADV212 data FIFOs. Two independent DMA channels can each be assigned to any one of the three data stream FIFOs (PIXEL, CODE, ATTR). The controller supports asynchronous DMA using a data-request/data-acknowledge (DREQ/DACK) protocol in either single or burst access modes. Additional functionality is provided for single address compatibility (fly-by) and dedicated chip select (DCS) modes. STAGE REGISTER Because the ADV212 contains both 16-bit and 32-bit registers and its internal memory is mapped as 32-bit data, a mechanism Rev. 0 | Page 27 of 44 ADV212 INTERNAL REGISTERS This section describes the internal registers of the ADV212. The host must first initialize the direct registers before any application-specific operation can be implemented. For additional information on accessing and configuring these registers, see the ADV212 User's Guide. DIRECT REGISTERS The ADV212 has 16 direct registers, as listed in Table 18. The direct registers are accessed over the ADDR [3:0], HDATA [31:0], CS, RD, WE, and ACK pins. Table 18. Direct Registers Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F Name PIXEL CODE ATTR Reserved CMDSTA EIRQIE EIRQFLG SWFLAG BUSMODE MMODE STAGE IADDR IDATA BOOT PLL_HI PLL_LO Description Pixel FIFO access register Compressed code stream access register Attribute FIFO access register Reserved Command stack External interrupt enabled External interrupt flags Software flag register Bus mode configuration register Miscellaneous mode register Staging register Indirect address register Indirect data register Boot mode register PLL control register--high byte PLL control register--low byte Rev. 0 | Page 28 of 44 ADV212 INDIRECT REGISTERS In certain modes, such as custom-specific input format or HIPI mode, indirect registers must be accessed by the user through the use of the IADDR and IDATA registers. The indirect register address space starts at Internal Address 0xFFFF0000. Both 32-bit and 16-bit hosts can access the indirect registers. 32-bit hosts use the IADDR and IDATA registers, and the 16-bit hosts use the IADDR, the IDATA, and the stage register. For additional information on accessing and configuring these registers, see the ADV212 User's Guide. Table 19. Indirect Registers Address 0xFFFF0400 0xFFFF0404 0xFFFF0408 0xFFFF040C 0xFFFF0410 0xFFFF0414 0xFFFF0418 0xFFFF041C 0xFFFF0420 0xFFFF0424 0xFFFF0428 0xFFFF042C 0xFFFF0430 0xFFFF0440 0xFFFF0444 0xFFFF0448 0xFFFF044C 0xFFFF1408 0xFFFF140C 0xFFFF1410 0xFFFF1414 0xFFFF1418 0xFFFF141C 0xFFFF1420 0xFFFF1424 to 0xFFFF14FC Name PMODE1 COMP_CNT_STATUS LINE_CNT_STATUS XTOT YTOT F0_START F1_START V0_START V1_START V0_END V1_END PIXEL_START PIXEL_END MS_CNT_DEL Reserved PMODE2 VMODE EDMOD0 EDMOD1 FFTHRP Reserved Reserved FFTHRC FFTHRA Reserved Description Pixel/video format Horizontal count Vertical count Total samples per line Total lines per frame Start line of Field 0 [F0] Start line of Field 1 [F1] Start of active video Field 0 [F0] Start of active video Field 1 [F1] End of active video Field 0 [F0] End of active video Field 1 [F1] Horizontal start of active video Horizontal end of active video Master/slave delay Reserved Pixel Mode 2 Video mode External DMA Mode Register 0 External DMA Mode Register 1 FIFO threshold for pixel FIFO Reserved Reserved FIFO threshold for code FIFO FIFO threshold for ATTR FIFO Reserved Rev. 0 | Page 29 of 44 ADV212 PLL The ADV212 uses the PLL_HI and PLL_LO direct registers to configure the PLL. Any time the PLL_LO register is modified, the host must wait at least 20 s before reading from or writing to another register. If this delay is not implemented, erratic behavior might result. MCLK is the input clock to the ADV212 PLL and is used to generate the internal JCLK (JPEG 2000 processor clock) and HCLK (embedded CPU clock). The PLL can be programmed to have any possible final multiplier value as long as * * * * * * * JCLK > 50 MHz and < 150 MHz (144-pin version). JCLK > 50 MHz and < 115 MHz (121-pin version). HCLK < 81 MHz (121-pin version), or HCLK < 108 MHz (144-pin version). JCLK 2 x VCLK for single-component input. JCLK 2 x VCLK for YCbCr [4:2:2] input. In JDATA mode (JDATA), JCLK must be 4 x MCLK or higher. The maximum burst frequency for external DMA modes is 0.36 JCLK. * * * * For MCLK frequencies greater than 50 MHz, the input clock divider must be enabled, that is, IPD must be set to 1. IPD cannot be enabled for MCLK frequencies below 20 MHz. Deinterlace modes require JCLK 4 x MCLK. It is not recommended to use an LLC output from a video decoder as a clock source for MCLK. To achieve the lowest power consumption, an MCLK frequency of 27 MHz is recommended for a standard definition CCIR 656 input. The PLL circuit is recommended to have a multiplier of 3. This sets JCLK and HCLK to 81 MHz. BYPASS IPD MCLK PHASE DETECT /2 LPF VCO /2 JCLK /2 /2 /PLLMULT /2 HCLKD LFB HCLK Figure 32. PLL Architecture and Control Functions Table 20. Recommended PLL Register Settings IPD 0 0 0 0 1 1 1 1 LFB 0 0 1 1 0 0 1 1 PLLMULT N N N N N N N N HCLKD 0 1 0 1 0 1 0 1 HCLK N x MCLK N x MCLK/2 2 x N x MCLK N x MCLK N x MCLK/2 N x MCLK/4 N x MCLK N x MCLK/2 JCLK N x MCLK N x MCLK 2 x N x MCLK 2 x N x MCLK N x MCLK/2 N x MCLK/2 N x MCLK N x MCLK Table 21. Recommended Values for PLL_HI and PLL_LO Registers Video Standard SMPTE 125M or ITU-R BT.656 (NTSC or PAL) SMPTE 293M (525p) ITU-R BT.1358 (625p) SMPTE 274M (1080i) CLKIN Frequency on MCLK 27 MHz 27 MHz 27 MHz 74.25 MHz PLL_HI 0x0008 0x0008 0x0008 0x0008 PLL_LO 0x0004 0x0004 0x0004 0x0084 Rev. 0 | Page 30 of 44 06389-009 ADV212 HARDWARE BOOT The boot mode can be configured via hardware using the CFG pins or via software. The first boot mode after power-up is set by the CFG pins. Table 22. Hardware Boot Modes Boot Mode Hardware Boot Mode 2 Hardware Boot Mode 4 Hardware Boot Mode 6 Settings CFG<1> tied high, CFG<2> tied low CFG<1> tied low, CFG<2> tied high CFG<1> and CFG<2> tied high Description No boot host mode. ADV212 does not boot, but all internal registers and memory are accessible through normal host input/output operations. Reserved. Reserved. Rev. 0 | Page 31 of 44 ADV212 VIDEO INPUT FORMATS The ADV212 supports a wide variety of formats for uncompressed video and still image data. The actual interface and bus modes selected for transferring uncompressed data dictates the allowed size of the input data and the number of samples transferred with each access. The host interface can support 8-/10-/12-/14-/16-bit data formats. The video interface can support video data or still image data input/output. Supported formats are 8-/10-/12-bit Table 23. Maximum Pixel Data Input Rates (144-Ball Package) Input Rate Limit Active Resolution (MSPS) 1 45 45 45 45 40 32 27 23 65 65 65 40 32 27 Approx Min Output Rate, Compressed Data 2 (Mbps) 130 130 130 130 130 130 130 130 130 130 130 130 130 130 Approx Max Output Rate, Compressed Data 3 (Mbps) 200 200 200 200 200 200 200 200 200 200 200 200 200 200 YCbCr formats or single component format. See the ADV212 User's Guide for details. All formats can support less precision than provided by specifying the actual data width/precision in the PMODE register. The maximum allowable data input rate is limited by using irreversible or reversible compression modes and the data width (or precision) of the input samples. Refer to Table 23 and Table 25 to determine the maximum data input rate. Interface HDATA VDATA Compression Mode Irreversible Irreversible Irreversible Irreversible Reversible Reversible Reversible Reversible Irreversible Irreversible Irreversible Reversible Reversible Reversible Input Format 8-bit data 10-bit data 12-bit data 16-bit data 8-bit data 10-bit data 12-bit data 14-bit data 8-bit data 10-bit data 12-bit data 8-bit data 10-bit data 12-bit data 1 2 Input rate limits for HDATA might be less for certain applications depending on input picture size and content, host interface settings, and DMA transfer settings. Minimum guaranteed sustained output rate or minimum sustainable compression rate [input rate/minimum peak output rate]. 3 Maximum peak output rate; an output rate above this value is not possible. Table 24. Maximum Pixel Data Input Rates (121-Ball Package) Input Rate Limit Active Resolution (MSPS) 1 34 34 34 34 30 24 20 17 48 48 48 30 24 20 Approx Min Output Rate, Compressed Data 2 (Mbps) 98 98 98 98 98 98 98 98 98 98 98 98 98 98 Approx Max Output Rate, Compressed Data 3 (Mbps) 150 150 150 150 150 150 150 150 150 150 150 150 150 150 Interface HDATA VDATA Compression Mode Irreversible Irreversible Irreversible Irreversible Reversible Reversible Reversible Reversible Irreversible Irreversible Irreversible Reversible Reversible Reversible Input Format 8-bit data 10-bit data 12-bit data 16-bit data 8-bit data 10-bit data 12-bit data 14-bit data 8-bit data 10-bit data 12-bit data 8-bit data 10-bit data 12-bit data 1 2 3 Input rate limits for HDATA might be less for certain applications depending on input picture size and content, host interface settings, and DMA transfer settings. Minimum guaranteed sustained output rate or minimum sustainable compression rate [input rate/minimum peak output rate]. Maximum peak output rate; an output rate above this value is not possible. Rev. 0 | Page 32 of 44 ADV212 Table 25. Maximum Supported Tile Width for Data Input on HDATA and VDATA Buses Compression Mode 9/7i 9/7i 9/7i 5/3i 5/3i 5/3i 5/3r 5/3r 5/3r Input Format Single-component Two-component Three-component Single-component Two-component Three-component Single-component Two-component Three-component Tile/Precinct Maximum Width 2048 1024 each 1024 (Y) 4096 2048 (each) 2048 (Y) 4096 2048 1024 Rev. 0 | Page 33 of 44 ADV212 APPLICATIONS This section describes typical video applications for the ADV212 JPEG 2000 video processor. In decode mode, a master/slave configuration (as shown in Figure 34) or a slave/slave configuration can be used to synchronize the outputs of the two ADV212s. See the AN-796 Application Note for details on how to configure the ADV212s in a multichip application. Applications that have two separate VDATA outputs sent to an FPGA or buffer before they are sent to an encoder do not require synchronization at the ADV212 outputs. 74.25MHz OSC ENCODE--MULTICHIP MODE Due to the data input rate limitation (see Table 23), an 1080i application requires at least two ADV212s to encode or decode full-resolution 1080i video. In encode mode, the ADV212 accepts Y and CbCr data on separate buses. An encode example is shown in Figure 33. 32-BIT HOST CPU DATA[31:0] ADDR[3:0] CS RD ACK WR IRQ DREQ DACK G I/O ADV212_1_SLAVE HDATA[31:0] ADDR[3:0] CS RD ACK WE IRQ DREQ DACK SCOMM[5] VCLK MCLK VDATA[11:2] FIELD VSYNC HSYNC ADV7402 10-BIT SD/HD VIDEO DECODER LLC 1080i VIDEO IN Y Y[9:0] CbCr C[9:0] ADV212_2_SLAVE HDATA[31:0] ADDR[3:0] CS RD WR ACK IRQ DREQ DACK CS RD WE ACK IRQ DREQ DACK SCOMM[5] HSYNC VSYNC FIELD VDATA[11:2] CbCr 06389-002 VCLK MCLK Figure 33. Encode--Multichip Application Rev. 0 | Page 34 of 44 ADV212 DECODE--MULTICHIP MASTER/SLAVE In a master/slave configuration, it is expected that the master HVF outputs are connected to the slave HVF inputs and that each SCOMM[5] pin is connected to the same GPIO on the host. 32-BIT HOST CPU DATA[31:0] ADDR[3:0] CS RD WR ACK IRQ DREQ DACK G I/O In a slave/slave configuration, the common HVF for both ADV212s is generated by an external house sync and each SCOMM[5] is connected to the same GPIO output on the host. SWIRQ1, Software Interrupt 1 in the EIRQIE register, must be unmasked on both devices to enable multichip mode. 74.25MHz OSC ADV212_1_MASTER HDATA[31:0] ADDR[3:0] CS RD WE ACK IRQ DREQ DACK SCOMM[5] VCLK MCLK VDATA[11:2] FIELD VSYNC HSYNC Y ADV7321A 10-BIT SD/HD VIDEO ENCODER CLKIN 1080i VIDEO OUT Y Y[9:0] CbCr C[9:0] ADV212_2_SLAVE HDATA[31:0] ADDR[3:0] CS RD WR ACK IRQ DREQ DACK CS RD WE ACK IRQ DREQ DACK SCOMM[5] HSYNC VSYNC FIELD VDATA[11:2] CbCr 06389-003 VCLK MCLK Figure 34. Decode--Multichip Master/Slave Application Rev. 0 | Page 35 of 44 ADV212 DIGITAL STILL CAMERA/CAMCORDER Figure 35 is a typical configuration for a digital camera or camcorder. AD9843A D[9:0] 10 FPGA DATA INPUTS[9:0] ADV212 MCLK VCLK VFRM VRDY VSTRB HDATA[15:0] ADDR[3:0] CS RD WE VDATA[15:6] ACK IRQ 16-BIT HOST CPU SDATA SCK SL SERIAL DATA SERIAL CLK SERIAL EN Figure 35. Digital Still Camera/Camcorder Encode Application for 10-Bit Pixel Data Using Raw Pixel Mode Rev. 0 | Page 36 of 44 06389-004 PIXEL OUT[9:0] DATA[15:0] ADDR[3:0] CS RD WE ACK IRQ ADV212 ENCODE/DECODE SDTV VIDEO APPLICATION Figure 36 shows two ADV212 chips using a 10-bit CCIR 656 in normal host mode. ENCODE MODE ADV212 ADV7189 10-BIT VIDEO DECODER VDATA[11:2] 32-BIT HOST CPU DATA[31:0] INTR ADDR[3:0] CS RD WE ACK HDATA[31:0] IRQ ADDR[3:0] CS RD WE ACK VCLK MCLK P[19:10] LLC1 27MHz OSC VIDEO IN DECODE MODE ADV212 ADV7301A 10-BIT VIDEO ENCODER VIDEO OUT VDATA[11:2] 32-BIT HOST CPU DATA[31:0] INTR ADDR[3:0] CS RD WE ACK HDATA[31:0] IRQ ADDR[3:0] CS RD WE ACK VCLK MCLK P[9:0] CLKIN 27MHz OSC Figure 36. Encode/Decode--SDTV Video Application Rev. 0 | Page 37 of 44 06389-005 ADV212 32-BIT HOST APPLICATION Figure 37 shows two ADV212 chips using a 10-bit CCIR 656 in normal host mode. FPGA ADV212 DREQ0 DACK0 DREQ0 DACK0 VDATA[11:2] HDATA[31:0] VCLK ADV7189 10-BIT VIDEO DECODER P[19:10] LLC1 27MHz OSC VIDEO IN DATA[31:0] 32-BIT HOST CPU DATA[31:0] IRQ ADDR[3:0] CS RD WE ACK IRQ ADDR[3:0] CS RD WE ACK MCLK ENCODE MODE FPGA ADV212 DREQ0 DACK0 DREQ0 DACK0 VDATA[11:2] HDATA[31:0] VCLK MCLK ADV730xA 10-BIT VIDEO ENCODER P[9:0] CLKIN VIDEO OUT DATA[31:0] 31-BIT HOST CPU DATA[31:0] IRQ ADDR[3:0] CS RD WE ACK IRQ ADDR[3:0] CS RD WE ACK 27MHz OSC DECODE MODE Figure 37. Encode/Decode 32-Bit Host Application Rev. 0 | Page 38 of 44 06389-006 ADV212 HIPI (HOST INTERFACE--PIXEL INTERFACE) Figure 38 is a typical configuration using HIPI mode. ADV212 Y0/G0 32-BIT HOST DATA<31:0> CS RD WR ACK IRQ DREQ DACK DREQ DACK CS RD WE ACK IRQ DREQ0 DACK0 DREQ1 DACK1 74.25MHz MCLK COMPRESSED DATA PATH RAW PIXEL DATA PATH 06389-007 Figure 38. Host Interface--Pixel Interface Mode Rev. 0 | Page 39 of 44 ADV212 JDATA INTERFACE Figure 39 shows a typical configuration using JDATA with a dedicated JDATA output, 16-bit host, and 10-bit CCIR 656. FPGA ADV212 JDATA[7:0] VDATA[11:2] HOLD FIELD VALID VSYNC HSYNC YCrCb ADV7189 P[19:10] FIELD VS HS VIDEO IN 16-BIT HOST CPU DATA[15:0] IRQ ADDR[3:0] CS RD WE ACK HDATA[15:0] IRQ ADDR[3:0] CS RD WE ACK VCLK LLC1 MCLK 27MHz OSC 06389-008 Figure 39. JDATA Application Rev. 0 | Page 40 of 44 ADV212 OUTLINE DIMENSIONS 12.20 12.00 SQ 11.80 A1 CORNER INDEX AREA 11 10 9 8 7 6 5 4 3 2 1 A B C D BALL A1 CORNER 10.00 BSC SQ 1.00 BSC E F G H J K L TOP VIEW BOTTOM VIEW *1.85 1.71 1.40 DETAIL A DETAILA 0.50 NOM 0.30 MIN 0.70 0.60 0.50 BALL DIAMETER *1.31 1.21 1.11 SEATING PLANE 0.20 COPLANARITY *COMPLIANT WITH JEDEC STANDARDS MO-192-ABD-1 WITH EXCEPTION TO PACKAGE HEIGHT AND THICKNESS. Figure 40. 121-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-121-1) Dimensions shown in millimeters A1 CORNER INDEX AREA 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M 13 .00 BSC SQ BALL A1 INDICATOR 11.00 BCS SQ TOP VIEW DETAIL A *1.85 MAX 1.00 BSC BOTTOM VIEW *1.32 1.21 1.11 DETAILA 0.53 0.43 0.70 0.60 0.50 BALL DIAMETER SEATING PLANE COPLANARITY 0.20 MAX *COMPLIANT WITH JEDEC STANDARDS MO-192-AAD-1 WITH EXCEPTION TO PACKAGE HEIGHT AND THICKNESS. Figure 41. 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-144-3) Dimensions shown in millimeters Rev. 0 | Page 41 of 44 021506-A 082406-A ADV212 ORDERING GUIDE Model ADV212BBCZ-115 1 ADV212BBCZRL-1151 ADV212BBCZ-1501 ADV212BBCZRL-1501 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C Speed Grade 115 MHz 115 MHz 150 MHz 150 MHz Operating Voltage 1.5 V Internal, 2.5 V or 3.3 V I/O 1.5 V Internal, 2.5 V or 3.3 V I/O 1.5 V Internal, 2.5 V or 3.3 V I/O 1.5 V Internal, 2.5 V or 3.3 V I/O Package Description 121-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 121-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] Package Option BC-121-1 BC-121-1 BC-144-3 BC-144-3 Z = Pb-free part. Rev. 0 | Page 42 of 44 ADV212 NOTES Rev. 0 | Page 43 of 44 ADV212 NOTES (c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06389-0-10/06(0) Rev. 0 | Page 44 of 44 |
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